1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of read- and write-accessing and operating the same.
2. Description of the Related Art
With an increase in capacity and packing density of a semiconductor memory device such as a dynamic random access memory (DRAM), a ratio of an area occupied by a capacitor to the remaining area in a memory cell is increased. For this reason, for example, in a 4-Mbit DRAM, a capacitor having a three-dimensional structure, such as a stacked capacitor or a trench capacitor, is used as a capacitor in a memory cell. Since a further increase in packing density of a memory device is expected, the structure of a memory cell will be increasingly complicated.
Under these circumstances, the use of ferroelectric materials having large dielectric constants, in place of conventional dielectric materials such as silicon oxides and nitrides, has been considered to simplify the structure of a capacitor. For example, lead zirconate titanate (PZT), a typical ferroelectric material, has a dielectric constant of 1,000 or more. Theoretically, therefore, a capacitor consisting of such a material can store a large amount of charge with a small area even if it has a planar structure. For this reason, it is expected that a semiconductor memory device obtained by using a ferroelectric material as a capacitor material allows a high packing density with a simple structure. A ferroelectric capacitor having a planar structure can be formed by a relatively simple process, i.e., sandwiching the upper and lower surfaces of a ferroelectric film deposited by sputtering or CVD between electrodes consisting of polysilicon or a metal.
In addition, manufacturing of a nonvolatile RAM by using ferroelectric capacitors is disclosed in, e.g., Published Unexamined Japanese Patent Application No. 63-201998. This memory is based on the fact that a relationship between the dielectric field and polarization of a ferroelectric material is represented by hysteresis characteristics. In a ferroelectric capacitor, even if an applied voltage becomes zero, a remanent polarization corresponding to the direction of the applied voltage is retained. If, therefore, the direction of remanent charge in an electrode is set to correspond to, e.g., "0" or "1", digital information can be stored in the ferroelectric capacitor.
In a ferroelectric capacitor, an applied voltage V and stored charge Q have a relationship shown in FIGS. 1A and 1B. FIG. 1A shows a Q-V curve observed at temperatures lower than the Curie temperature (ferroelectric phase). FIG. 1B shows a Q-V curve observed at temperature higher than the Curie temperature (normal dielectric phase).
FIG. 2 shows a conventional memory cell formed by combining such a ferroelectric capacitor with a MOS transistor. FIG. 3 is a partial circuit diagram showing a semiconductor memory device for writing and reading information of 1 bit in and from such a memory cell.
In the memory cell shown in FIG. 2, a word line (WL) 104 is connected to the gate electrode of a MOS transistor 117, the source and drain of the MOS transistor 117 are respectively connected to a bit line (BL) 116 and one electrode of a ferroelectric capacitor 118, and the other electrode of the ferroelectric capacitor 118 is connected to a plate line (PL) 113. The plate line 113 and the word line 104 are formed to be parallel with each other. Furthermore, in the semiconductor memory device shown in FIG. 3, two bit lines (BL) 116-1 and (BL) 116-2 connected to one sense amplifier (S/A) 120 constitute a bit line pair and are formed on both sides of the sense amplifier 120.
The structure shown in FIG. 3 is considered as one column. A plurality of columns, each having the same structure as that shown in FIG. 3, are arranged in the Y direction (parallel to the length of the paper) to constitute a memory cell (rows are arranged along the X direction parallel to the width of the paper) array. FIG. 4 is a circuit diagram of the memory cell array. A word line 104 is connected to the gate electrodes of MOS transistors 117 of a plurality of memory cells arranged in the same row, which are arranged in the Y direction (the X direction is perpendicular to the Y direction). The word line 104 is also connected to a word line decoder 119. The plate line 113 is connected to the electrodes of ferroelectric capacitors 118 of the memory cells in the same row and is also connected to a plate line decoder 128.
In a read or write cycle in such a memory cell array, the word line 104 and plate line 113 of the same row are respectively selected by the word line decoder 119 and the plate line decoder 128. If, for example, a word line WL2 is selected, a plate line PL2 of the same row is selected in the corresponding cycle.
That is, when the single word line WL2 and the corresponding plate line PL2 are selected, the memory cells, of all the columns, connected to these lines are simultaneously selected. The pieces of digital information of these memory cells are extracted through the bit lines 116-1 or 116-2. In the semiconductor memory device, once information is read out, the information stored in a corresponding memory cell is erased. If, therefore, information in a memory cell is to be retained after a read operation, information identical to the readout digital information must be written in the memory cell again. That is, a rewrite operation must be performed.
For this reason, a flip-flop type amplifier is normally used as a sense amplifier. FIG. 5 shows a typical sense amplifier constituted by complementary MOS transistors. A sense amplifier 120 of this type is activated in accordance with a sense amplifier activating signal input through a sense amplifier activating line (ACT) 149-1 or (ACT) 149-2 so as to amplify a small potential difference between the bit lines 116-1 and 116-2. With this operation, the potentials of the bit lines are determined such that one potential of power source voltages of the sense amplifier, e.g., V.sub.SS and V.sub.CC, is transferred to one bit line; and the other potential, to the other bit line.
In the semiconductor memory device having the conventional structure shown in FIG. 4, once a word line and a plate line are selected, the pieces of digital information of all the memory cells connected to these lines are extracted through bit lines, and all the sense amplifiers are activated. Once a sense amplifier is selected, the potentials of a corresponding bit line pair are changed. After one cycle is completed, the bit lines must be precharged within a preparation period before an access operation. For this reason, in the semiconductor memory device having the conventional structure shown in FIG. 4, the power consumed to activate the sense amplifiers and charge/discharge the bit lines is inevitably increased. In addition, with regard to a precharge operation of bit lines, since the charge quantity required to charge/discharge operations is increased with an increase in the number of bits, the time required to charge/discharge the bit lines is inevitably prolonged.
The above-described arrangement and operation are similar to those of a dynamic random access memory (DRAM). In a DRAM, when a word line is selected by a row address, the pieces of information stored in all the memory cells connected to the word line are respectively extracted through bit lines connected to the respective memory cells. For this reason, all the sense amplifiers connected to the bit lines through which the pieces of information are extracted from the memory cells are activated regardless of whether they are selected by column addresses. With this operation, sensing operations of the bit lines are performed. As a result, a rewrite operation of the stored information in the memory cells is performed. Such a rewrite operation is performed because a DRAM is constituted by destructive read type memory cells unlike an DRAM.
Three problems, i.e., a decrease in operation speed, an increase in power consumption, and generation of noise due to a charge/discharge operation of charge in/from all the bit lines, will be described below with reference to a DRAM.
For example, a 1-Mbit DRAM having a cycle time of 200 ns and an average current of 60 mA in an active period will be considered. In this 1-Mbit DRAM, the capacitance c of one bit line is about 0.6 pF. As described above, in the DRAM, 2048 bit lines are charged/discharged by a voltage V with an amplitude of 5 V in one access operation. In this case, a required charge quantity Q is given by ##EQU1## If the resultant value is divided by a cycle T time of 200 nS, an average current I is provided: ##EQU2## This indicates that about 50% of the average current in an active period is used for a bit line charge/discharge operation. Of the average current in an active period, the proportion of a bit line charge/discharge current tends to be increased as the capacity of the DRAM is increased, e.g., from 1 Mbit to 4 and 16 Mbits.
In the 1-Mbit DRAM, the total capacitance of the bit lines which must be charged/discharged in each access operation is 0.6 (pF) .times.2,048 (lines) =1.2 (nF), and a large current peak appears when a charge/discharge operation of the capacitance is performed at once. That is, a current of 60 mA in an active period does not flow constantly but substantially concentrates in a period in which a bit line charge/discharge operation is performed. An abrupt change dI/dt of this current causes variations in power source voltages, e.g., V.sub.CC and V.sub.SS, together with inductances inside/outside a chip. Power source noise generated in this manner leads to erroneous operations of circuits in the chip or to cause the ground level of logic "0" of output information to float, thus causing undesired operations.
In order to perform a rewrite or precharge operation with respect to all the bit lines in every access operation, a large capacitance of 1.2 (nF) must be charged/discharged. The time required for such a charge/discharge operation is determined by this capacitance, the wiring resistances of aluminum wires, and the ON resistances of transistors. In a 1-Mbit DRAM, for example, of a cycle time of 200 ns, about 100 ns, i.e., about 50% of the cycle time, is consumed for a bit line charge/discharge operation.
In the conventional semiconductor memory device shown in FIG. 4, since all the bit lines are charged/discharged in an access operation, the problems of a decrease in operation speed, an increase in power consumption, and generation of noise are posed, similar to the above-described DRAM. In the semiconductor device shown in FIG. 4, when a given plate line is selected, and its potential is changed, a corresponding word line is always selected. Assume that the level of a plate line is changed from L level to H level. In this case, as the charges stored in ferroelectric capacitors in the row direction are discharged to the bit lines, the ferroelectric capacitors act as loads for the plate line. That is, the capacitance of all the ferroelectric capacitors connected to the plate line acts as a load for the plate line decoder. This capacitance is large in comparison with the gate capacitance of a MOS transistor acting as a main load for a word line. For this reason, the plate line decoder requires a driving capacity larger than that of the word line decoder. Otherwise, it takes much time to charge a plate line capacitance, and the time required for an access operation is further prolonged.
In addition, as described above, in the conventional semiconductor memory device shown in FIG. 4, when one memory cell is to be accessed, all the memory cells of the same row are simultaneously accessed. The charges of the memory cells are then extracted to bit lines, and a rewrite operation must be performed. In a ferroelectric capacitor, that information is read out and written means that polarization reversal occurs at a 50% probability. That is, one of the stored information of "1" and "0" undergoes polarization reversal in an access operation. In a ferroelectric capacitor, it is known that as polarization reversal is repeated, the remnant polarization, i.e., the amount of charge stored in the electrode in a nonvolatile manner, is reduced. For example, in a semiconductor memory device having 1,024 memory cells connected to one word line, every time one memory cell is read-accessed, each of the remaining 1,023 memory cells is set in a state wherein the polarization of a corresponding ferroelectric capacitor can be reversed and is reversed at a 50% probability. In the worst case, the polarizations of all the 1,023 ferroelectric capacitors are reversed. As described above, in a semiconductor memory device constituted by such conventional ferroelectric capacitors, there is a possibility that the polarizations of the ferroelectric capacitors of all the memory cells in the same row are reversed. This accelerates a deterioration in dielectric characteristics of each ferroelectric capacitor and shortens the service life of the semiconductor memory device.
In the semiconductor memory device using the ferroelectric capacitors shown in FIG. 4, a memory cell can be constituted by one MOS transistor and one ferroelectric capacitor. Such a structure, therefore, is suitable for a large-capacity semiconductor memory device. In addition, the method of operating the memory device using the ferroelectric capacitors is similar to that of a DRAM in many respects, e.g., rewriting information in the ferroelectric capacitor of a memory cell by amplifying the potential of a corresponding bit line by using a flip-flop type sense amplifier. Therefore, many of the circuit techniques for DRAMs can be directly applied to the semiconductor memory device using the ferroelectric capacitors. In addition, this semiconductor memory device is superior to a DRAM in that it theoretically requires no refresh operation and is nonvolatile.
In the semiconductor memory device using such ferroelectric capacitors, however, a problem associated with refresh characteristics (to be described in detail below) is posed, even though no refresh operation is theoretically required as described above. In practice, therefore, refresh operations are required, although its frequency is not so high as that in a DRAM.
In DRAMs, a problem is posed in terms of leakage currents which lead to a decrease in charge stored in the capacitor of each memory cell over time. Such leakage currents include, e.g., a p-n Junction leakage current flowing between a storage node and a semiconductor substrate, a sub-threshold current from an access transistor, a leakage current from a parasitic field transistor, and a leakage current from a capacitor dielectric film. Of these leakage currents, the problem is mainly associated with the p-n Junction leakage current. Such leakage occurs when carriers such as electrons and holes are thermally generated in a depletion layer of a p-n junction between the source of drain of a MOS transistor and a semiconductor substrate, and the carriers are moved upon application of an electric field to the depletion layer. In a DRAM, different potentials, e.g., 5 V and 0 V are applied to a storage node depending on whether charge is stored in the capacitor of a memory cell. In a DRAM, since such a potential is reduced to a thermal equilibrium state due to leakage currents over time, a refresh operation is required.
In contrast to this, in the semiconductor memory device using the ferroelectric capacitors, if the two ends of a ferroelectric capacitor can be maintained at the same potential, the information stored in the memory cell is retained, and no refresh operation is required. If, however, similar to a DRAM, a bias potential is applied to a semiconductor substrate in order to reduce the capacitance of each bit line, and a reverse bias is applied to a depletion layer between the source of drain of a transistor and the semiconductor substrate, the potential of the storage node of a corresponding memory cell approaches the substrate potential over time, resulting in a potential difference between the two ends of a corresponding ferroelectric capacitor. This is because electrons and holes thermally generated in the depletion layer receive an electrostatic force due to an electric field in the depletion layer and are attracted to the source or drain of the transistor and the substrate. In the semiconductor memory device using such ferroelectric capacitors, therefore, refresh operations are required, although its frequency is not so high as that in a DRAM.
Similar to a DRAM, in such a semiconductor memory device, the problem of erroneous operations based on soft errors is posed. A soft error means that the contents stored in a memory cell are volatiled by a particles emitted from radioactive elements, such as uranium and thorium, contained in a package in a small amount. An a particle enters the semiconductor substrate by a distance of about several tens micrometers, and an electron-hole pair of about 200 fC are generated along the path of the .alpha. particle. When the charge generated in this manner flows into the storage node of a memory cell or a bit line upon diffusion and movement, the stored information is volatiled. As described above, a soft error volatiles the information stored in a memory cell to cause an erroneous operation. As a result, reliability of the semiconductor memory device is greatly deteriorated. In a conventional DRAM, however, there is no method of completely eliminating such soft errors. Furthermore, in the semiconductor memory device using the ferroelectric capacitors, no method has been developed, which can eliminate soft errors.
As described above, in the semiconductor memory device using the ferroelectric capacitors, there are various problems, e.g., a decrease in operation speed, an increase in power consumption, generation of noise, and shortening of a service life. Therefore, such a memory device has not yet been put into practical use.
In the semiconductor memory device using the ferroelectric capacitors, similar to a DRAM, refresh operations are required, and erroneous operations are caused by soft errors. In addition, such a semiconductor memory device, the refresh characteristics and reliability tend to be deteriorated with a decrease in amount of charge stored in each ferroelectric capacitor. That is, the above-described problems become more serious as the capacitance of each ferroelectric capacitor is decreased. Therefore, such problems interfere with an increase in packing density of a semiconductor memory device.